24LCS52集成電路（IC）的存儲(chǔ)器規(guī)格書PDF中文資料

24LCS52屬于集成電路（IC）的存儲(chǔ)器。由微芯科技股份有限公司制造生產(chǎn)的24LCS52存儲(chǔ)器存儲(chǔ)器是集成電路上用作數(shù)據(jù)存儲(chǔ)設(shè)備的半導(dǎo)體器件。這些器件分為非易失性或易失性兩種，格式包括 CBRAM、DRAM、EEPROM、EERAM、EPROM、閃存、FRAM、NVSRAM、PCM (PRAM)、PSRAM、RAM 和 SRAM。這些器件的存儲(chǔ)容量為 64 b 至 6 Tb 不等，接口有 I2C、MMC、并行、eMMC、串行、單線、SPI、UFS、Xccela 總線和 1-線。

Description:

The Microchip Technology Inc. 24AA52/24LCS52 (24XXX52*) is a 2 Kbit Electrically Erasable PROM capable of operation across a broad voltage range (1.8V to 5.5V). This device has a software write-protect feature for the lower half of the array, as well as an external pin that can be used to write-protect the entire array. The software write-protect feature is enabled by sending the device a special command. Once this feature has been enabled, it cannot be reversed. In addition to the software protect feature, there is a WP pin that can be used to write-protect the entire array, regardless of whether the software write-protect register has been written or not. This allows the system designer to protect none, half, or all of the array, depending on the application.

Features:

? Single Supply with Operation Down to 1.8V

? Low-Power CMOS Technology:

- 1 mA active current, typical

- 1 μA standby current, typical (I-temp)

? Organized as 1 Block of 256 Bytes (256 x 8)

? Software Write Protection for Lower 128 Bytes

? Hardware Write Protection for Entire Array

? 2-Wire Serial Interface Bus, I2C? Compatible

? Schmitt Trigger Inputs for Noise Suppression

? Output Slope Control to Eliminate Ground Bounce

? 100 kHz (24AA52) and 400 kHz (24LCS52) Compatibility

? Self-Timed Write Cycle (including auto-erase)

? Page Write Buffer for up to 16 Bytes

? ESD Protection > 4,000V

? 1,000,000 Erase/Write Cycles

? Data Retention > 200 Years

? 8-Lead PDIP, SOIC, TSSOP, MSOP, DFN and TDFN Packages

? Pb-Free Finishes Available

? Available for Extended Temperature Ranges:

- Industrial (I): -40°C to +85°C