72V2113L15PFBCG8中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

FEATURES:

? Choose among the following memory organizations:

IDT72V2103 ? 131,072 x 18/262,144 x 9

IDT72V2113 ? 262,144 x 18/524,288 x 9

? Functionally compatible with the IDT72V255LA/72V265LA and

IDT72V275/72V285 SuperSync FIFOs

? Up to 166 MHz Operation of the Clocks

? User selectable Asynchronous read and/or write ports (BGA Only)

? 6 ns read/write cycle time (4.0 ns access time)

? User selectable input and output port bus-sizing

- x9 in to x9 out

- x9 in to x18 out

- x18 in to x9 out

- x18 in to x18 out

? Big-Endian/Little-Endian user selectable byte representation

? 5V tolerant inputs

? Fixed, low first word latency

? Zero latency retransmit

? Auto power down minimizes standby power consumption

? Master Reset clears entire FIFO

? Partial Reset clears data, but retains programmable settings