74AUP1G17GW集成電路（IC）的緩沖器驅動器接收器收發(fā)器規(guī)格書PDF中文資料

廠商型號	74AUP1G17GW
參數屬性	74AUP1G17GW 封裝/外殼為5-TSSOP，SC-70-5，SOT-353；包裝為卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶；類別為集成電路（IC）的緩沖器驅動器接收器收發(fā)器；產品描述：IC BUF NON-INVERT 3.6V 5TSSOP
功能描述	Low-power Schmitt trigger
絲印標識	PJ
封裝外殼	SOT353-1 / 5-TSSOP，SC-70-5，SOT-353
文件大小	321.24 Kbytes
頁面數量	24 頁
生產廠商	Nexperia B.V. All rights reserved
企業(yè)簡稱	NEXPERIA【安世】
中文名稱	安世半導體(中國)有限公司官網
原廠標識
數據手冊	下載地址一下載地址二到原廠下載
更新時間	2025-3-14 23:00:00
人工找貨	74AUP1G17GW價格和庫存，歡迎聯系客服免費人工找貨

1. General description

The 74AUP1G17 is a single buffer with Schmitt-trigger input. This device ensures very low static

and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is

fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output,

preventing the potentially damaging backflow current through the device when it is powered down.

2. Features and benefits

? Wide supply voltage range from 0.8 V to 3.6 V

? CMOS low power dissipation

? High noise immunity

? Overvoltage tolerant inputs to 3.6 V

? Low noise overshoot and undershoot < 10 of VCC

? IOFF circuitry provides partial Power-down mode operation

? Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

? Low static power consumption; ICC = 0.9 μA (maximum)

? Complies with JEDEC standards:

? JESD8-12 (0.8 V to 1.3 V)

? JESD8-11 (0.9 V to 1.65 V)

? JESD8-7 (1.2 V to 1.95 V)

? JESD8-5 (1.8 V to 2.7 V)

? JESD8C (2.7 V to 3.6 V)

? ESD protection:

? HBM: ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 5000 V

? CDM: ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 1000 V

? MM: JESD22-A115-A exceeds 200 V

? Multiple package options

? Specified from -40 ° C to +85 ° C and -40 ° C to +125 ° C