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74AUP1G32GZ-Q100中文資料安世數(shù)據(jù)手冊PDF規(guī)格書

74AUP1G32GZ-Q100
廠商型號

74AUP1G32GZ-Q100

功能描述

Low-power 2-input OR-gate

絲印標識

pG

封裝外殼

XSON5

文件大小

259.3 Kbytes

頁面數(shù)量

16

生產(chǎn)廠商 Nexperia B.V. All rights reserved
企業(yè)簡稱

NEXPERIA安世

中文名稱

安世半導(dǎo)體(中國)有限公司官網(wǎng)

原廠標識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2025-3-29 23:00:00

人工找貨

74AUP1G32GZ-Q100價格和庫存,歡迎聯(lián)系客服免費人工找貨

74AUP1G32GZ-Q100規(guī)格書詳情

1. General description

The 74AUP1G32-Q100 provides the single 2-input OR function.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times

across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range

from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry

disables the output, preventing the damaging backflow current through the device when it is

powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

? Automotive product qualification in accordance with AEC-Q100 (Grade 1)

? Specified from -40 °C to +85 °C and from -40 °C to +125 °C

? Wide supply voltage range from 0.8 V to 3.6 V

? High noise immunity

? Complies with JEDEC standards:

? JESD8-12 (0.8 V to 1.3 V)

? JESD8-11 (0.9 V to 1.65 V)

? JESD8-7 (1.2 V to 1.95 V)

? JESD8-5 (1.8 V to 2.7 V)

? JESD8-B (2.7 V to 3.6 V)

? Low static power consumption; ICC = 0.9 μA (maximum)

? Latch-up performance exceeds 100 mA per JESD 78 Class II

? Inputs accept voltages up to 3.6 V

? Low noise overshoot and undershoot < 10 % of VCC

? IOFF circuitry provides partial power-down mode operation

? ESD protection:

? HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V

? CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

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