74AUP2G126集成電路（IC）的緩沖器驅(qū)動器接收器收發(fā)器規(guī)格書PDF中文資料

廠商型號	74AUP2G126
參數(shù)屬性	74AUP2G126 封裝/外殼為8-XFDFN；包裝為管件；類別為集成電路（IC）的緩沖器驅(qū)動器接收器收發(fā)器；產(chǎn)品描述：IC BUFFER NON-INVERT 3.6V 8XSON
功能描述	Low-power dual buffer/line driver; 3-state
封裝外殼	8-XFDFN
文件大小	325.13 Kbytes
頁面數(shù)量	23 頁
生產(chǎn)廠商	Nexperia B.V. All rights reserved
企業(yè)簡稱	NEXPERIA【安世】
中文名稱	安世半導體(中國)有限公司官網(wǎng)
原廠標識
數(shù)據(jù)手冊	下載地址一下載地址二到原廠下載
更新時間	2025-5-28 8:30:00
人工找貨	74AUP2G126價格和庫存，歡迎聯(lián)系客服免費人工找貨

1. General description

The 74AUP2G126 is a dual buffer/line driver with 3-state outputs controlled by the output enable

inputs (nOE). Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and

fall times. This device ensures very low static and dynamic power consumption across the entire

VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

2. Features and benefits

? Wide supply voltage range from 0.8 V to 3.6 V

? High noise immunity

? CMOS low power dissipation

? Low static power consumption; ICC = 0.9 μA (maximum)

? Latch-up performance exceeds 100 mA per JESD78 Class II

? Overvoltage tolerant inputs to 3.6 V

? Low noise overshoot and undershoot < 10 of VCC

? Input-disable feature allows floating input conditions

? IOFF circuitry provides partial Power-down mode operation

? Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

? Complies with JEDEC standards:

? JESD8-12 (0.8 V to 1.3 V)

? JESD8-11 (0.9 V to 1.65 V)

? JESD8-7 (1.2 V to 1.95 V)

? JESD8-5 (1.8 V to 2.7 V)

? JESD8C (2.7 V to 3.6 V)

? ESD protection:

? HBM JESD22-A114F Class 3A exceeds 5000 V

? MM JESD22-A115-A exceeds 200 V

? CDM JESD22-C101E exceeds 1000 V

? Multiple package options

? Specified from -40 °C to +85 °C and -40 °C to +125 °C