74HC4514PW集成電路（IC）的信號(hào)開(kāi)關(guān)多路復(fù)用器解碼器規(guī)格書(shū)PDF中文資料

1. General description

The 74HC4514; 74HCT4514 is a 4-to-16 line decoder/demultiplexer having four binary weighted

address inputs (A0 to A3), with latches, a latch enable input (LE), an enable input (E) and

16 outputs (Q0 to Q15). When LE is HIGH, the selected output is determined by the data on An.

When LE goes LOW, the last data present at An are stored in the latches and the outputs remain

stable. When E is LOW, the selected output, determined by the contents of the latch, is HIGH.

At E HIGH, all outputs are LOW. The enable input E does not affect the state of the latch. When

the device is used as a demultiplexer, E is the data input and A0 to A3 are the address inputs.

Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to

voltages in excess of VCC.

The 74HCT4514 features reduced input threshold levels to allow interfacing to TTL logic levels.

2. Features and benefits

? Wide supply voltage range from 2.0 to 6.0 V

? CMOS low power dissipation

? High noise immunity

? Input levels:

? For 74HC4514: CMOS level

? For 74HCT4514: TTL level

? 16-line demultiplexing capability

? Decodes 4 binary-coded inputs into 16 mutually-exclusive outputs

? Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

? Complies with JEDEC standards

? JESD8C (2.7 V to 3.6 V)

? JESD7A (2.0 V to 6.0 V)

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

? Specified from -40 °C to +85 °C and -40 °C to +125 °C

3. Applications

? Digital multiplexing

? Address decoding

? Hexadecimal/BCD decoding