74HCT373PW集成電路（IC）的鎖存器規(guī)格書PDF中文資料

General description

The 74HC373; 74HCT373 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.

The 74HC373; 74HCT373 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all latches.

The 74HC373; 74HCT373 consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D input changes.

When LE is LOW the latches store the information that was present at the D inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches.

The 74HC373; 74HCT373 is functionally identical to:

? 74HC563; 74HCT563: but inverted outputs and different pin arrangement

? 74HC573; 74HCT573: but different pin arrangement

Features and benefits

■ 3-state non-inverting outputs for bus oriented applications

■ Common 3-state output enable input

■ Functionally identical to the 74HC563; 74HCT563 and 74HC573; 74HCT573

■ ESD protection:

◆ HBM JESD22-A114F exceeds 2 000 V

◆ MM JESD22-A115-A exceeds 200 V

■ Specified from -40 °C to +85 °C and from -40 °C to +125 °C