74LS191中文資料仙童半導(dǎo)體數(shù)據(jù)手冊PDF規(guī)格書

General Description

The DM74LS191 circuit is a synchronous, reversible, up/down counter. Synchronous operation is provided by having all flip-flops clocked simultaneously, so that the outputs change simultaneously when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters.

Features

■ Counts binary

■ Single down/up count control line

■ Count enable control input

■ Ripple clock output for cascading

■ Asynchronously presettable with load control

■ Parallel outputs

■ Cascadable for n-bit applications

■ Average propagation delay 20 ns

■ Typical clock frequency 25 MHz

■ Typical power dissipation 100 mW