74LVC1G240GM集成電路（IC）的緩沖器驅(qū)動器接收器收發(fā)器規(guī)格書PDF中文資料

廠商型號	74LVC1G240GM
參數(shù)屬性	74LVC1G240GM 封裝/外殼為6-XFDFN；包裝為管件；類別為集成電路（IC）的緩沖器驅(qū)動器接收器收發(fā)器；產(chǎn)品描述：74LVC1G240GM/SOT886/XSON6
功能描述	Single inverting buffer/line driver; 3-state
絲印標識	V2
封裝外殼	SOT886 / 6-XFDFN
文件大小	233.47 Kbytes
頁面數(shù)量	14 頁
生產(chǎn)廠商	Nexperia B.V. All rights reserved
企業(yè)簡稱	NEXPERIA【安世】
中文名稱	安世半導體(中國)有限公司官網(wǎng)
原廠標識
數(shù)據(jù)手冊	下載地址一下載地址二到原廠下載
更新時間	2025-2-19 18:26:00

1. General description

The 74LVC1G240 is a 1-bit inverting buffer/line driver with 3-state output. The device features

an output enable OE. A HIGH on OE causes the output to assume a high-impedance OFF-state.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices

as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

2. Features and benefits

? Wide supply voltage range from 1.65 V to 5.5 V

? High noise immunity

? Complies with JEDEC standard:

? JESD8-7 (1.65 V to 1.95 V)

? JESD8-5 (2.3 V to 2.7 V)

? JESD8-B/JESD36 (2.7 V to 3.6 V)

? ±24 mA output drive (VCC = 3.0 V)

? ESD protection:

? ? HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2000 V

? CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 1000 V

? CMOS low power consumption

? Inputs accept voltages up to 5 V

? Latch-up performance exceeds 250 mA

? Direct interface with TTL levels

? Specified from -40 °C to +85 °C and -40 °C to +125 °C