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74LVC1G86-Q100_V01中文資料安世數(shù)據(jù)手冊(cè)PDF規(guī)格書

74LVC1G86-Q100_V01
廠商型號(hào)

74LVC1G86-Q100_V01

功能描述

2-input EXCLUSIVE-OR gate

文件大小

220.76 Kbytes

頁(yè)面數(shù)量

11 頁(yè)

生產(chǎn)廠商 Nexperia B.V. All rights reserved
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NEXPERIA安世

中文名稱

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數(shù)據(jù)手冊(cè)

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更新時(shí)間

2025-2-11 20:00:00

74LVC1G86-Q100_V01規(guī)格書詳情

1. General description

The 74LVC1G86-Q100 provides the 2-input EXCLUSIVE-OR function.

Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these

devices in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry

disables the output, preventing the damaging backflow current through the device when it is

powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

? Automotive product qualification in accordance with AEC-Q100 (Grade 1)

? Specified from -40 °C to +85 °C and -40 °C to +125 °C

? Wide supply voltage range from 1.65 V to 5.5 V

? High noise immunity

? Overvoltage tolerant inputs to 5.5 V

? Complies with JEDEC standard:

? JESD8-7 (1.65 V to 1.95 V)

? JESD8-5 (2.3 V to 2.7 V)

? JESD8C (2.7 V to 3.6 V)

? JESD36 (4.5 V to 5.5 V)

? ±24 mA output drive (VCC = 3.0 V)

? CMOS low power dissipation

? IOFF circuitry provides partial Power-down mode operation

? Latch-up performance exceeds 250 mA

? Direct interface with TTL levels

? ESD protection:

? HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

? CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

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