74LVC244ABQ集成電路（IC）的緩沖器驅(qū)動器接收器收發(fā)器規(guī)格書PDF中文資料

廠商型號	74LVC244ABQ
參數(shù)屬性	74LVC244ABQ 封裝/外殼為20-VFQFN 裸露焊盤；包裝為卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶；類別為集成電路（IC）的緩沖器驅(qū)動器接收器收發(fā)器；產(chǎn)品描述：IC BUF NON-INVERT 3.6V 20DHVQFN
功能描述	Octal buffer/line driver; 3-state
封裝外殼	20-VFQFN 裸露焊盤
文件大小	286.14 Kbytes
頁面數(shù)量	17 頁
生產(chǎn)廠商	Nexperia B.V. All rights reserved
企業(yè)簡稱	NEXPERIA【安世】
中文名稱	安世半導體(中國)有限公司官網(wǎng)
原廠標識
數(shù)據(jù)手冊	下載地址一下載地址二到原廠下載
更新時間	2025-2-16 13:00:00

1. General description

The 74LVC244A; 74LVCH244A are 8-bit buffer/line drivers with 3-state outputs. The devices can

be used as two 4-bit buffers or one 8-bit buffer. Both devices features two output enables (1OE and

2OE), each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume

a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature

allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

2. Features and benefits

? Wide supply voltage range from 1.2 V to 3.6 V

? CMOS low-power consumption

? Direct interface with TTL levels

? Overvoltage tolerant inputs to 5.5 V

? IOFF circuitry provdes partial Power-down mode operation

? Bus hold on all data inputs (74LVCH244A only)

? Complies with JEDEC standard:

? JESD8-7A (1.65 V to 1.95 V)

? JESD8-5A (2.3 V to 2.7 V)

? JESD8-C/JESD36 (2.7 V to 3.6 V)

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115B exceeds 200 V

? CDM JESD22-C101E exceeds 1000 V

? Specified from -40 °C to +85 °C and -40 °C to +125 °C