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74LVC595APW集成電路(IC)的移位寄存器規(guī)格書PDF中文資料

74LVC595APW
廠商型號

74LVC595APW

參數(shù)屬性

74LVC595APW 封裝/外殼為16-TSSOP(0.173",4.40mm 寬);包裝為卷帶(TR)剪切帶(CT)Digi-Reel? 得捷定制卷帶;類別為集成電路(IC)的移位寄存器;產品描述:IC 8BIT SHIFT REGISTER 16-TSSOP

功能描述

8-bit serial-in/serial-out or parallel-out shift register; 3-state

封裝外殼

16-TSSOP(0.173",4.40mm 寬)

文件大小

299.94 Kbytes

頁面數(shù)量

18

生產廠商 Nexperia B.V. All rights reserved
企業(yè)簡稱

NEXPERIA安世

中文名稱

安世半導體(中國)有限公司官網(wǎng)

原廠標識
數(shù)據(jù)手冊

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更新時間

2025-2-21 19:07:00

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74LVC595APW規(guī)格書詳情

1. General description

The 74LVC595A is an 8-bit serial-in/serial or parallel-out shift register with a storage register and

3-state outputs. Both the shift and storage register have separate clocks. The device features a

serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR

input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions

of the SHCP input. The data in the shift register is transferred to the storage register on a

LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register

will always be one clock pulse ahead of the storage register. Data in the storage register appears

at the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs

to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of

the registers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use

of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all

inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for

partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the

potentially damaging backflow current through the device when it is powered down.

2. Features and benefits

? Wide supply voltage range from 1.2 V to 3.6 V

? Overvoltage tolerant inputs to 5.5 V

? CMOS low power dissipation

? Direct interface with TTL levels

? IOFF circuitry provides partial Power-down mode operation

? Balanced propagation delays

? All inputs have Schmitt-trigger action

? Complies with JEDEC standard:

? JESD8-7A (1.65 V to 1.95 V)

? JESD8-5A (2.3 V to 2.7 V)

? JESD8-C/JESD36 (2.7 V to 3.6 V)

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-B exceeds 200 V

? CDM JESD22-C101E exceeds 1000 V

? Specified from -40 °C to +85 °C and -40 °C to +125 °C

3. Applications

? Serial-to-parallel data conversion

? Remote control holding register

產品屬性

  • 產品編號:

    74LVC595APW,118

  • 制造商:

    Nexperia USA Inc.

  • 類別:

    集成電路(IC) > 移位寄存器

  • 系列:

    74LVC

  • 包裝:

    卷帶(TR)剪切帶(CT)Digi-Reel? 得捷定制卷帶

  • 邏輯類型:

    移位寄存器

  • 輸出類型:

    三態(tài)

  • 功能:

    串行至并行,串行

  • 電壓 - 供電:

    1.65V ~ 3.6V

  • 工作溫度:

    -40°C ~ 125°C

  • 安裝類型:

    表面貼裝型

  • 封裝/外殼:

    16-TSSOP(0.173",4.40mm 寬)

  • 供應商器件封裝:

    16-TSSOP

  • 描述:

    IC 8BIT SHIFT REGISTER 16-TSSOP

供應商 型號 品牌 批號 封裝 庫存 備注 價格
NEXPERIA/安世
21+
NA
12820
只做原裝,質量保證
詢價
NXP
13+
TSSOP
877
一級代理,專注軍工、汽車、醫(yī)療、工業(yè)、新能源、電力
詢價
TI
24+
標準
43735
熱賣原裝進口
詢價
Nexperia
22+
TSSOP
6868
全新正品現(xiàn)貨 有掛就有現(xiàn)貨
詢價
NXP/恩智浦
24+
TSSOP-16
9800
只做原裝正品現(xiàn)貨或訂貨假一賠十!
詢價
NXP(恩智浦)
23+
9865
原裝正品,假一賠十
詢價
NXP/恩智浦
22+
TSSOP
54157
只做原裝進口現(xiàn)貨
詢價
NEXPERIA/安世
21+
NA
195000
只做原裝,假一罰十
詢價
NXP/恩智浦
24+
SOIC-14_150mil
30000
原裝正品公司現(xiàn)貨,假一賠十!
詢價
NXP/恩智浦
22+
TSSOP
20000
原裝現(xiàn)貨,實單支持
詢價