首頁(yè)>74LVCH16374A-Q100>規(guī)格書詳情
74LVCH16374A-Q100中文資料安世數(shù)據(jù)手冊(cè)PDF規(guī)格書
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廠商型號(hào) |
74LVCH16374A-Q100 |
功能描述 | 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state |
文件大小 |
230.64 Kbytes |
頁(yè)面數(shù)量 |
14 頁(yè) |
生產(chǎn)廠商 | Nexperia B.V. All rights reserved |
企業(yè)簡(jiǎn)稱 |
NEXPERIA【安世】 |
中文名稱 | 安世半導(dǎo)體(中國(guó))有限公司官網(wǎng) |
原廠標(biāo)識(shí) | ![]() |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2025-2-19 17:57:00 |
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74LVCH16374A-Q100規(guī)格書詳情
General description
The 74LVC16374A-Q100 and 74LVCH16374A-Q100 are 16-bit edge-triggered flip-flops featuring separate D-type inputs with bus hold (74LVCH16374A-Q100 only) for each flip-flop and 3-state outputs for bus-oriented applications. It consists of two sections of eight positive edge-triggered flip-flops. A clock input (nCP) and an output enable (nOE) are provided for each octal.
The flip-flops store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition.
When pin nOE is LOW, the contents of the flip-flops are available at the outputs. When pin nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of input nOE does not affect the state of the flip-flops.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications.
Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
? Automotive product qualification in accordance with AEC-Q100 (Grade 1)
? Specified from -40 °C to +85 °C and from -40 °C to +125 °C
? 5 V tolerant inputs/outputs for interfacing with 5 V logic
? Wide supply voltage range from 1.2 V to 3.6 V
? CMOS low power consumption
? Multibyte flow-through standard pinout architecture
? Low inductance multiple supply pins for minimum noise and ground bounce
? Direct interface with TTL levels
? All data inputs have bus hold (74LVCH16374A-Q100 only)
? High-impedance outputs when VCC = 0 V
? Complies with JEDEC standard:
? JESD8-7A (1.65 V to 1.95 V)
? JESD8-5A (2.3 V to 2.7 V)
? JESD8-C/JESD36 (2.7 V to 3.6 V)
? ESD protection:
? MIL-STD-883, method 3015 exceeds 2000 V
? HBM JESD22-A114F exceeds 2000 V
? MM JESD22-A115-A exceeds 200 V (C = 200 pF; R = 0 ?)
供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
PHILIPS |
24+ |
TSOP48 |
21322 |
公司原廠原裝現(xiàn)貨假一罰十!特價(jià)出售!強(qiáng)勢(shì)庫(kù)存! |
詢價(jià) | ||
NXP |
23+ |
SOP |
3200 |
全新原裝、誠(chéng)信經(jīng)營(yíng)、公司現(xiàn)貨銷售 |
詢價(jià) | ||
PHI |
TSSOP48 |
68500 |
一級(jí)代理 原裝正品假一罰十價(jià)格優(yōu)勢(shì)長(zhǎng)期供貨 |
詢價(jià) | |||
NEXPERIA/安世 |
2023+ |
8700 |
原裝現(xiàn)貨 |
詢價(jià) | |||
TI&BB |
24+ |
TSSOP48 |
2789 |
原裝優(yōu)勢(shì)!絕對(duì)公司現(xiàn)貨! |
詢價(jià) | ||
IDT |
23+ |
SSOP |
6372 |
原廠授權(quán)代理,海外優(yōu)勢(shì)訂貨渠道??商峁┐罅繋?kù)存,詳 |
詢價(jià) | ||
NXP/恩智浦 |
1535+ |
8478 |
詢價(jià) | ||||
PHI |
01+ |
TSSOP/48 |
559 |
原裝現(xiàn)貨海量庫(kù)存歡迎咨詢 |
詢價(jià) | ||
IDT |
23+ |
SSOP |
3200 |
專營(yíng)高頻管模塊,全新原裝! |
詢價(jià) | ||
IDT |
22+ |
SSOP56 |
21498 |
原裝正品現(xiàn)貨,可開(kāi)13個(gè)點(diǎn)稅 |
詢價(jià) |