74LVQ573MTR集成電路（IC）的鎖存器規(guī)格書(shū)PDF中文資料

74LVQ573MTR屬于集成電路（IC）的鎖存器。由意法半導(dǎo)體集團(tuán)制造生產(chǎn)的74LVQ573MTR鎖存器鎖存器是類(lèi)似于觸發(fā)器的基本數(shù)字存儲(chǔ)設(shè)備，但是不同之處在于，在鎖存使能（或類(lèi)似命名）信號(hào)處于有效邏輯狀態(tài)的任何時(shí)間，保持的邏輯狀態(tài)都可以改變?！巴该鳌辨i存器還允許設(shè)備輸出在鎖存使能信號(hào)有效時(shí)反映輸入的當(dāng)前狀態(tài)，而相反的是，狀態(tài)僅在保持狀態(tài)已固定時(shí)改變。

DESCRIPTION

The 74LVQ573 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED:

tPD = 5.8 ns (TYP.) at VCC = 3.3 V

■ COMPATIBLE WITH TTL OUTPUTS

■ LOW POWER DISSIPATION:

ICC = 4 μA (MAX.) at TA=25°C

■ LOW NOISE:

VOLP = 0.5V (TYP.) at VCC = 3.3V

■ 75? TRANSMISSION LINE DRIVING CAPABILITY

■ SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 12mA (MIN) at VCC = 3.0 V

■ PCI BUS LEVELS GUARANTEED AT 24 mA

■ BALANCED PROPAGATION DELAYS: tPLH ? tPHL

■ OPERATING VOLTAGE RANGE:

VCC(OPR) = 2V to 3.6V (1.2V Data Retention)

■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573

■ IMPROVED LATCH-UP IMMUNITY