74V2G74中文資料意法半導(dǎo)體數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The 74V2G74 is an advanced high-speed CMOS SINGLE D-TYPE FLIP FLOP WITH PRESET AND CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology.

A signal on the D INPUT is transfered to the Q and Q OUTPUTS during the positive going transition of the clock pulse.

CLEAR and PRESET are independent of the clock and accomplished by a low setting on the appropriate input.

Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them ESD immunity and transient excess voltage.

■ HIGH SPEED: fMAX = 170 MHz (TYP.) at VCC = 5V

■ LOW POWER DISSIPATION: ICC = 1 μA (MAX.) at TA=25°C

■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN.)

■ POWER DOWN PROTECTION ON INPUTS

■ SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN)

■ BALANCED PROPAGATION DELAYS: tPLH ? tPHL

■ OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V

■ FUNCTION COMPATIBLE WITH 74 SERIES 74

■ IMPROVED LATCH-UP IMMUNITY