74VHC573SJ集成電路（IC）的鎖存器規(guī)格書(shū)PDF中文資料

74VHC573SJ屬于集成電路（IC）的鎖存器。由安森美半導(dǎo)體公司制造生產(chǎn)的74VHC573SJ鎖存器鎖存器是類(lèi)似于觸發(fā)器的基本數(shù)字存儲(chǔ)設(shè)備，但是不同之處在于，在鎖存使能（或類(lèi)似命名）信號(hào)處于有效邏輯狀態(tài)的任何時(shí)間，保持的邏輯狀態(tài)都可以改變?！巴该鳌辨i存器還允許設(shè)備輸出在鎖存使能信號(hào)有效時(shí)反映輸入的當(dāng)前狀態(tài)，而相反的是，狀態(tài)僅在保持狀態(tài)已固定時(shí)改變。

The MC74VHC573 is an advanced high speed CMOS octal latch with 3?state output fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.

This 8?bit D?type latch is controlled by a latch enable input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state.

The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.

? High Speed: tPD = 4.5ns (Typ) at VCC = 5V

? Low Power Dissipation: ICC = 4μA (Max) at TA = 25°C

? High Noise Immunity: VNIH = VNIL = 28 VCC

? Power Down Protection Provided on Inputs

? Balanced Propagation Delays

? Designed for 2V to 5.5V Operating Range

? Low Noise: VOLP = 1.2V (Max)

? Pin and Function Compatible with Other Standard Logic Families

? Latchup Performance Exceeds 300mA

? ESD Performance: HBM > 2000V; Machine Model > 200V

? Chip Complexity: 218 FETs or 54.5 Equivalent Gates

These devices are available in Pb?free package(s). Specifications herein

apply to both standard and Pb?free devices. Please see our website at

www.onsemi.com for specific Pb?free orderable part numbers, or

contact your local ON Semiconductor sales office or representative.