74VHCT595PW集成電路（IC）的移位寄存器規(guī)格書PDF中文資料

1. General description

The 74VHC595; 74VHCT595 are high-speed Si-gate CMOS devices and are pin compatible with

Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A.

The 74VHC595; 74VHCT595 are 8-stage serial shift registers with a storage register and 3-state

outputs. The shift registers have separate clocks.

Data is shifted on the positive-going transitions of the shift register clock input (SHCP). The data

in each register is transferred to the storage register on a positive-going transition of the storage

register clock input (STCP). If both clocks are connected together, the shift register will always be

one clock pulse ahead of the storage register.

The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading. It is

also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage

register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output

whenever the output enable input (OE) is LOW.

2. Features and benefits

? Balanced propagation delays

? All inputs have Schmitt-trigger action

? Inputs accept voltages higher than VCC

? Input levels:

? For 74VHC595: CMOS level

? For 74VHCT595: TTL level

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-A exceeds 200 V

? CDM JESD22-C101E exceeds 1000 V

? Multiple package options

? Specified from -40 °C to +85 °C and from -40 °C to +125 °C

3. Applications

? Serial-to-parallel data conversion

? Remote control holding register