79RC32438中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

Features

◆ 32-bit CPU Core

– MIPS32 instruction set

– Cache Sizes: 16KB instruction and data caches, 4-Way set

associative, cache line locking, non-blocking prefetches

– 16 dual-entry JTLB with variable page sizes

– 3-entry instruction TLB

– 3-entry data TLB

– Max issue rate of one 32x16 multiply per clock

– Max issue rate of one 32x32 multiply every other clock

– CPU control with start, stop and single stepping

– Software breakpoints support

– Hardware breakpoints on virtual addresses

– Enhanced JTAG and ICE Interface that is compatible with v2.5

of the EJTAG Specification

◆ DDR Memory Controller

– Supports up to 2GB of DDR SDRAM

– 2 chip selects (each chip select supports 4 internal DDR

banks)

– Supports 16-bit or 32-bit data bus width using 8, 16, or 32-bit

devices

– Supports 64Mb, 128Mb, 256Mb, 512Mb, and 1Gb DDR

SDRAM devices

– Data bus multiplexing support allows interfacing to standard

DDR DIMMs and SODIMMs

– Automatic refresh generation

◆ Memory and Peripheral Device Controller

– Provides “glueless” interface to standard SRAM, Flash, ROM,

dual-port memory, and peripheral devices

– Demultiplexed address and data buses: 16-bit data bus, 26-bit

address bus, 6 chip selects, supports alternate bus masters,

control for external data bus buffers

– Supports 8-bit and 16-bit width devices

Automatic byte gathering and scattering

– Flexible protocol configuration parameters: programmable

number of wait states (0 to 63), programmable postread/postwrite

delay (0 to 31), supports external wait state generation,

supports Intel and Motorola style peripherals

– Write protect capability per chip select

– Programmable bus transaction timer generates warm reset

when counter expires

– Supports up to 64 MB of memory per chip select

◆ Counter/Timers

– Three general purpose 32-bit counter timers

◆ PCI Interface

– 32-bit PCI revision 2.2 compliant (3.3V only)

– Supports host or satellite operation in both master and target

modes

– Support for synchronous and asynchronous operation

– PCI clock supports frequencies from 16 MHz to 66 MHz

– PCI arbiter in Host mode: supports 6 external masters, fixed

priority or round robin arbitration

– I2O “l(fā)ike” PCI Messaging Unit