844S012I-01中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

Features

? Two differential LVDS outputs (Bank A), configurable for PCIe

(100MHz or 250MHz) and sRIO (100MHz or 125MHz) clock

signals

? Eight LVCMOS/LVTTL outputs (Bank B/C), 18? typical output

impedance

? Two REF_OUT LVCMOS/LVTTL clock outputs 23? typical output

impedance

? Selectable crystal oscillator interface, 25MHz, 18pF parallel

resonant crystal or one LVCMOS/LVTTL single-ended reference

clock input

? Supports the following output frequencies:

LVDS Bank A: 100MHz, 125MHz, 200MHz and 250MHz

LVCMOS/LVTTL Bank B/C: 33.33MHz, 50MHz, 66.67MHz,

100MHz, 125MHz, 133.33MHz, 166.67MHz and 200MHz

? VCO: 2GHz

? Spread spectrum clock: ±0.25 center-spread, and

-0.6 down-spread

? PLL bypass and output enable

? RMS period jitter: 23ps (maximum), QB outputs

? Full 3.3V supply voltage

? -40°C to 85°C ambient operating temperature

? Available in a lead-free (RoHS 6) compliant package