8543AG-09LF中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

Features

? Four differential LVDS output pairs

? Selectable differential CLK, nCLK or LVPECL clock inputs

? CLK, nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

? PCLK, nPCLK supports the following input types:

LVPECL, CML, SSTL

? Maximum output frequency: 800MHz

? Translates any single-ended input signal to LVDS levels with

resistor bias on nCLK input

? Additive phase jitter, RMS: 0.146ps (typical)

? Output skew: 100ps (maximum)

? Part-to-part skew: 700ps (maximum)

? Propagation delay: 3.3ns (maximum)

? Full 3.3V supply mode

? 0°C to 70°C ambient operating temperature

? Available in lead-free (RoHS 6) package

? Industrial temperature information available upon request