87608I中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

FEATURES

? Fully integrated PLL

? Eight LVCMOS/LVTTL outputs, 15Ω typical output impedance

? Selectable crystal oscillator interface or

LVCMOS/LVTTL REF_IN clock input

? Maximum output frequency: 166.67MHz

? Maximum crystal input frequency: 38MHz

? Maximum REF_IN input frequency: 41.67MHz

? Individual banks with selectable output dividers for

generating 33.333MHz, 66.66MHz, 100MHz and

133.333MHz

? Separate feedback control for generating PCI / PCI-X

frequencies from a 16.66MHz or 20MHz crystal, or 25MHz

or 33.33MHz reference frequency

? VCO range: 200MHz to 500MHz

? Cycle-to-cycle jitter: 120ps (maximum), @ 3.3V

? Period jitter, RMS: 20ps (maximum)

? Output skew: 250ps (maximum)

? Bank skew: 60ps (maximum)

? Static phase offset: 160ps ± 160ps

? Voltage Supply Modes:

VDD (core/inputs), VDDA (analog supply for PLL),

VDDOA (output bank A),

VDDOB (output bank B, REF_OUT, FB_OUT)

VDD/VDDA/VDDOA/VDDOB

3.3/3.3/3.3/3.3

3.3/3.3/2.5/3.3

3.3/3.3/3.3/2.5

3.3/3.3/2.5/2.5

? -40°C to 85°C ambient operating temperature

? Available in lead-free RoHS compliant package