8KS2564GAHA04中文資料英飛凌數(shù)據(jù)手冊(cè)PDF規(guī)格書

Features

? Interface

- HYPERBUS? extended-IO

- 1.7 to 2.0 V (1.8 typ.) interface support

? Single-ended clock (CK) - 20 bus signals

? Optional differential clock (CK, CK#) - 21 bus signals

- Chip Select (CS#)

- 16-bit data bus (DQ[15:0])

- Hardware reset (RESET#)

- Bidirectional read-write data strobe (RWDS [1:0])

? Output at the start of all transactions to indicate refresh latency

? Output during read transactions as read data strobe

? Input during write transactions as write data mask

? Performance, power, and packages

- 200 MHz maximum clock rate

- DDR - transfers data on both edges of the clock

- Data throughput up to 800 MBps (6,400 Mbps)

- Configurable burst characteristics

? Linear burst

? Wrapped burst lengths:

16 words (8 clocks)

32 words (16 clocks)

64 words (32 clocks)

128 words (64 clocks)

? Hybrid option - one wrapped burst followed by linear burst

- Configurable output drive strength

- Power modes

? Hybrid Sleep mode

? Deep Power Down

- Memory array refresh

? Partial array (1/8, 1/4, 1/2, and so on)

? Full array

- Package

? 49-ball FBGA

- Operating temperature range

? Automotive, AEC-Q100 Grade 3: –40°C to +85°C

? Automotive, AEC-Q100 Grade 2: –40°C to +105°C

? Technology

- 25 nm DRAM