8SLVP2108ANLGISLASHW中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

Description

The 8SLVP2108 is a high-performance differential dual 1:8

LVPECL fanout buffer. The device is designed for the fanout of

high-frequency, very low additive phase-noise clock and data

signals.

The 8SLVP2108 is characterized to operate from a 3.3V or 2.5V

power supply. Guaranteed output-to-output and part-to-part skew

characteristics make the 8SLVP2108 ideal for those clock

distribution applications demanding well-defined performance and

repeatability. Two independent buffers with eight low skew outputs

each are available. The integrated bias voltage references enable

easy interfacing of single-ended signals to the device inputs. The

device is optimized for low power consumption and low additive

phase noise.

Features

? Two 1:8, low skew, low additive jitter LVPECL fanout buffers

? Two differential clock inputs

? Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can

accept the following differential input levels: LVDS, LVPECL,

CML

? Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can

also accept single-ended LVCMOS levels. See Applications

section Wiring the Differential Input Levels to Accept

Single-ended Levels (Figure 1A and Figure 1B).

? Maximum input clock frequency: 2GHz

? Output bank skew: 15ps (typical)

? Propagation delay: 390ps (maximum)

? Low additive phase jitter, RMS: 54fs (maximum)

(fREF = 156.25MHz, VPP = 1V, 12kHz – 20MHz, VCC = 3.3V)

? Full 3.3V and 2.5V supply voltage

? Maximum device current consumption (IEE): 143mA

? Available in Lead-free (RoHS 6), 48-Lead VFQFN package

? Supports case temperature ??105°C operations

? -40°C to 85°C ambient operating temperature