ACS161HMSR中文資料Intersil數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Description

The Intersil ACS161MS is a Radiation Hardened 4-Bit Binary Synchronous Counter. The MR is an active low master reset. SPE is an active low Synchronous Parallel Enable which disables counting and allows data at the preset inputs (P0 - P3) to load the counter. CP is the positive edge clock. TC is the terminal count or carry output. Both TE and PE must be high for counting to occur, but are irrelevant to loading. TE low will keep TC low.

Features

? Devices QML Qualified in Accordance with MIL-PRF-38535

? Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96706 and Intersil’ QM Plan

? 1.25 Micron Radiation Hardened SOS CMOS

? Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)

? Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day (Typ)

? SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg

? Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse

? Dose Rate Survivability. . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse

? Latch-Up Free Under Any Conditions

? Military Temperature Range . . . . . . . . . . . . . . . . . . -55°C to +125°C

? Significant Power Reduction Compared to ALSTTL Logic

? DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V

? Input Logic Levels

??? - VIL = 30 of VCC Max

??? - VIH = 70 of VCC Min

? Input Current ≤ 1μA at VOL, VOH

? Fast Propagation Delay . . . . . . . . . . . . . . . . 21ns (Max), 14ns (Typ)