AD5689集成電路（IC）的數(shù)模轉(zhuǎn)換器（DAC）規(guī)格書PDF中文資料

AD5689屬于集成電路（IC）的數(shù)模轉(zhuǎn)換器（DAC）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD5689數(shù)模轉(zhuǎn)換器（DAC）數(shù)模轉(zhuǎn)換器（DAC、D/A、D2A 或 D 轉(zhuǎn) A）可將數(shù)字信號(hào)轉(zhuǎn)換為緩沖或無緩沖的模擬電壓或電流。DAC 架構(gòu)是否適合特定應(yīng)用，要取決于分辨率和采樣頻率。DAC 通常用于音樂播放器，將數(shù)字?jǐn)?shù)據(jù)流轉(zhuǎn)換為模擬音頻流。它們還用于電視和手機(jī)，將數(shù)字視頻數(shù)據(jù)轉(zhuǎn)換為模擬視頻信號(hào)，再連接到屏幕驅(qū)動(dòng)器，以顯示單色或彩色圖像。

GENERAL DESCRIPTION

The AD5689/AD5687 members of the nanoDAC+? family are low power, dual, 16-/12-bit, buffered voltage output digital-to-analog converters (DACs). The devices include a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The AD5689/AD5687 operate from a single 2.7 V to 5.5 V supply, are guaranteed monotonic by design, and exhibit less than 0.1 FSR gain error and 1.5 mV offset error performance. Both devices are available in a 3 mm × 3 mm LFCSP and a TSSOP package.

FEATURES

High relative accuracy (INL): ±2 LSB maximum at 16 bits

Tiny package: 3 mm × 3 mm, 16-lead LFCSP

TUE: ±0.1 of FSR maximum

Offset error: ±1.5 mV maximum

Gain error: ±0.1 of FSR maximum

High drive capability: 20 mA, 0.5 V from supply rails

User-selectable gain of 1 or 2 (GAIN pin)

Reset to zero scale or midscale (RSTSEL pin)

1.8 V logic compatibility

50 MHz SPI with readback or daisy chain

Low glitch: 0.5 nV-sec

Low power: 3.3 mW at 3 V

2.7 V to 5.5 V power supply

?40°C to +105°C temperature range

APPLICATIONS

Optical transceivers

Base station power amplifiers

Process control (PLC I/O cards)

Industrial automation

Data acquisition systems