AD7194BCPZ集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）規(guī)格書(shū)PDF中文資料

AD7194BCPZ屬于集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD7194BCPZ模數(shù)轉(zhuǎn)換器（ADC）模數(shù)轉(zhuǎn)換器（ADC、A/D 或 A 轉(zhuǎn) D）對(duì)模擬信號(hào)進(jìn)行采樣，例如由麥克風(fēng)采集的聲音或傳感器的輸出，然后將其轉(zhuǎn)換為數(shù)字信號(hào)。一般來(lái)說(shuō)，數(shù)字輸出是二進(jìn)制補(bǔ)碼二進(jìn)制數(shù)，與輸入成比例。輸入類型可能是差分、偽差分或單端輸入。模數(shù)轉(zhuǎn)換器可按照位數(shù)、采樣率、輸入數(shù)、接口、轉(zhuǎn)換器數(shù)和架構(gòu)（例如自適應(yīng)增量、雙斜率、折疊、流水線、SAR、三角積分、兩步式）進(jìn)行選擇。

GENERAL DESCRIPTION

The AD7194 is a low noise, complete analog front end for high precision measurement applications. It contains a low noise, 24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC). The on-chip low noise gain stage means that signals of small amplitude can interface directly to the ADC.

FEATURES

Fast settling filter option

8 differential/16 pseudo differential input channels

RMS noise: 11 nV at 4.7 Hz (gain = 128)

15.5 noise-free bits at 2.4 kHz (gain = 128)

Up to 22 noise-free bits (gain = 1)

Offset drift: ±5 nV/°C

Gain drift: ±1 ppm/°C

Programmable gain (1 to 128)

Output data rate: 4.7 Hz to 4.8 kHz

Internal or external clock

Simultaneous 50 Hz/60 Hz rejection

4 general-purpose digital outputs

Power supply

AVDD: 3 V to 5.25 V

DVDD: 2.7 V to 5.25 V

Current: 4.65 mA

Temperature range: ?40°C to +105°C

Package: 32-lead LFCSP

Interface

3-wire serial

SPI, QSPI?, MICROWIRE?, and DSP compatible

Schmitt trigger on SCLK

APPLICATIONS

PLC/DCS analog input modules

Data acquisition

Strain gage transducers