AD7721SQ中文資料亞德諾數(shù)據(jù)手冊PDF規(guī)格書

GENERAL DESCRIPTION

The AD7721 is a complete low power, 12-/16-bit, sigma-delta ADC. The part operates from a +5 V supply and accepts a differential input of 0 V to 2.5 V or ±1.25 V. The analog input is continuously sampled by an analog modulator at twice the clock frequency eliminating the need for external sample-andhold circuitry. The modulator output is processed by two finite impulse response (FIR) digital filters in series. The on-chip filtering reduces the external antialias requirements to first orde in most cases. Settling time for a step input is 97.07 μs while the group delay for the filter is 48.53 μs when the master clock equals 15 MHz.

FEATURES

16-Bit Sigma-Delta ADC

468.75 kHz Output Word Rate (OWR)

No Missing Codes

Low-Pass Digital Filter

High Speed Serial Interface

Linear Phase

229.2 kHz Input Bandwidth

Power Supplies: AVDD, DVDD: +5 V ± 5

Standby Mode (70 μW)

Parallel Mode (12-Bit/312.5 kHz OWR)