AD8158ACPZ集成電路（IC）的信號(hào)開(kāi)關(guān)多路復(fù)用器解碼器規(guī)格書(shū)PDF中文資料

AD8158ACPZ屬于集成電路（IC）的信號(hào)開(kāi)關(guān)多路復(fù)用器解碼器。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD8158ACPZ信號(hào)開(kāi)關(guān)，多路復(fù)用器，解碼器邏輯型信號(hào)開(kāi)關(guān)、多路復(fù)用器和編碼器 IC 可用于對(duì)以數(shù)字格式表示數(shù)據(jù)的電信號(hào)進(jìn)行路由和選擇。這些器件與設(shè)計(jì)用于模擬信號(hào)的類(lèi)似產(chǎn)品有所不同，它們保留的信息表示為兩個(gè)電狀態(tài)之一，而不是兩個(gè)外部界限內(nèi)的無(wú)窮變化量。

GENERAL DESCRIPTION

The AD8158 is an asynchronous, protocol-agnostic, quad-lane 2:1 switch with a total of 12 differential CML inputs and 12 differential CML outputs. The signal path supports NRZ signaling with data rates up to 6.5 Gbps per lane. Each lane offers programmable receive equalization, programmable output pre-emphasis, programmable output levels, and loss-of signal detection.

FEATURES

Quad 2:1 mux/1:2 demux

Optimized for dc to 6.5 Gbps NRZ data

Per-lane P/N pair inversion for routing ease

Programmable input equalization

Compensates up to 40 inches of FR4

Loss-of-signal detection

Programmable output pre-emphasis up to 12 dB

Programmable output levels with squelch and disable

Accepts ac-coupled or dc-coupled differential CML inputs

50 Ω on-chip termination

1:2 demux supports unicast or bicast operation

Port-level loopback

Port or single lane switching

1.8 V to 3.3 V flexible core supply

User-settable I/O supply from VCC to 1.2 V

Low power, typically 2.0 W in basic configuration

100-lead LFCSP

?40°C to +85°C operating temperature range

APPLICATIONS

Low cost redundancy switch

SONET OC48/SDH16 and lower data rates

XAUI/GbE/FC/Infiniband over backplane

OIF CEI 6.25 Gbps over backplane

Serial data-level shift

4-/8-/12-lane equalizers or redrivers