AD9211開發(fā)板套件編程器的評(píng)估板-模數(shù)轉(zhuǎn)換器（ADC）規(guī)格書PDF中文資料

AD9211屬于開發(fā)板套件編程器的評(píng)估板-模數(shù)轉(zhuǎn)換器（ADC）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9211評(píng)估板 - 模數(shù)轉(zhuǎn)換器（ADC）模數(shù)轉(zhuǎn)換器 (ADC) 評(píng)估板是預(yù)裝有元器件的電路板，用于提供特定 ADC 或器件工作實(shí)例。特定板上的 A/D 轉(zhuǎn)換器數(shù)量從 3 到 32 不等，每秒采樣率從 2.5 kHz 到 26 GHz 不等，輸入電壓范圍從 0 到 8 Vp-p。

GENERAL DESCRIPTION

The AD9211 is a 10-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 300 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete

signal conversion solution.

FEATURES

SNR = 60.1 dBFS @ fIN up to 70 MHz @ 300 MSPS

ENOB of 9.7 @ fIN up to 70 MHz @ 300 MSPS (?1.0 dBFS)

SFDR = ?80 dBc @ fIN up to 70 MHz @ 300 MSPS (?1.0 dBFS)

Excellent linearity

DNL = ±0.1 LSB typical

INL = ±0.2 LSB typical

LVDS at 300 MSPS (ANSI-644 levels)

700 MHz full power analog bandwidth

On-chip reference, no external decoupling required

Integrated input buffer and track-and-hold

Low power dissipation

437 mW @ 300 MSPS—LVDS SDR mode

410 mW @ 300 MSPS—LVDS DDR mode

Programmable input voltage range 1.0 V to 1.5 V, 1.25 V nominal

1.8 V analog and digital supply operation

Selectable output data format (offset binary, twos complement, Gray code)

Clock duty cycle stabilizer

Integrated data capture clock

APPLICATIONS

Wireless and wired broadband communications

Cable reverse path

Communications test equipment

Radar and satellite subsystems

Power amplifier linearization