AD9233BCPZ-105集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）規(guī)格書PDF中文資料

AD9233BCPZ-105屬于集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9233BCPZ-105模數(shù)轉(zhuǎn)換器（ADC）模數(shù)轉(zhuǎn)換器（ADC、A/D 或 A 轉(zhuǎn) D）對模擬信號進(jìn)行采樣，例如由麥克風(fēng)采集的聲音或傳感器的輸出，然后將其轉(zhuǎn)換為數(shù)字信號。一般來說，數(shù)字輸出是二進(jìn)制補碼二進(jìn)制數(shù)，與輸入成比例。輸入類型可能是差分、偽差分或單端輸入。模數(shù)轉(zhuǎn)換器可按照位數(shù)、采樣率、輸入數(shù)、接口、轉(zhuǎn)換器數(shù)和架構(gòu)（例如自適應(yīng)增量、雙斜率、折疊、流水線、SAR、三角積分、兩步式）進(jìn)行選擇。

GENERAL DESCRIPTION

The AD9233 is a monolithic, single 1.8 V supply, 12-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC), featuring a high performance sample-and-hold amplifier (SHA) and on-chip voltage reference. The product uses a multistage differential pipeline architecture with output error correction logic to provide 12-bit accuracy at 125 MSPS data rates and guarantees no missing codes over the full operating temperature range.

FEATURES

1.8 V analog supply operation

1.8 V to 3.3 V output supply

SNR = 69.5 dBc (70.5 dBFS) to 70 MHz input

SFDR = 85 dBc to 70 MHz input

Low power: 395 mW @ 125 MSPS

Differential input with 650 MHz bandwidth

On-chip voltage reference and sample-and-hold amplifier

DNL = ±0.15 LSB

Flexible analog input: 1 V p-p to 2 V p-p range

Offset binary, Gray code, or twos complement data format

Clock duty cycle stabilizer

Data output clock

Serial port control

Built-in selectable digital test pattern generation

Programmable clock and data alignment

APPLICATIONS

Ultrasound equipment

IF sampling in communications receivers

IS-95, CDMA-One, IMT-2000

Battery-powered instruments

Hand-held scopemeters

Low cost digital oscilloscopes