AD9253BCPZ-105集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）規(guī)格書PDF中文資料

AD9253BCPZ-105屬于集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）。由亞德諾半導體技術有限公司制造生產(chǎn)的AD9253BCPZ-105模數(shù)轉(zhuǎn)換器（ADC）模數(shù)轉(zhuǎn)換器（ADC、A/D 或 A 轉(zhuǎn) D）對模擬信號進行采樣，例如由麥克風采集的聲音或傳感器的輸出，然后將其轉(zhuǎn)換為數(shù)字信號。一般來說，數(shù)字輸出是二進制補碼二進制數(shù)，與輸入成比例。輸入類型可能是差分、偽差分或單端輸入。模數(shù)轉(zhuǎn)換器可按照位數(shù)、采樣率、輸入數(shù)、接口、轉(zhuǎn)換器數(shù)和架構（例如自適應增量、雙斜率、折疊、流水線、SAR、三角積分、兩步式）進行選擇。

GENERAL DESCRIPTION

The AD9253 is a quad, 14-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC) with an on-chip sample and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.

FEATURES

1.8 V supply operation

Low power: 110 mW per channel at 125 MSPS with scalable power options

SNR = 74 dB (to Nyquist)

SFDR = 90 dBc (to Nyquist)

DNL = ±0.75 LSB (typical); INL = ±2.0 LSB (typical)

Serial LVDS (ANSI-644, default) and low power, reduced signal option (similar to IEEE 1596.3)

650 MHz full power analog bandwidth

2 V p-p input voltage range

Serial port control

Full chip and individual channel power-down modes

Flexible bit orientation

Built-in and custom digital test pattern generation

Multichip sync and clock divider

Programmable output clock and data alignment

Programmable output resolution

Standby mode

APPLICATIONS

Medical ultrasound

High speed imaging

Quadrature radio receivers

Diversity radio receivers

Test equipment