AD9520-5/PCBZ開發(fā)板套件編程器的評估演示板及套件規(guī)格書PDF中文資料

AD9520-5/PCBZ屬于開發(fā)板套件編程器的評估演示板及套件。由亞德諾半導體技術有限公司制造生產的AD9520-5/PCBZ評估和演示板及套件該系列產品提供了一種方便的方法，在經過驗證的實施環(huán)境中評估某些重點器件的性能或特性。評估方法通常有完善的文檔說明，并且視乎具體情況由評估軟件提供支持。產品通常由印刷電路板組成，板上已裝有重點器件以及必要或有用的支持元器件，另外也可能包括其他組件，例如電纜或電源。對于數(shù)量特別多或類別獨特的器件類別(如 ADC、DAC 和開關模式電源)，評估平臺可組合為一個單獨的產品系列。

GENERAL DESCRIPTION

The AD9520-51 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL that can be used with an external VCO.

The AD9520-5 serial interface supports both SPI and I2C ports. An in-package EEPROM, which can be programmed through the serial interface, can store user-defined register settings for power-up and chip reset.

The AD9520-5 features 12 LVPECL outputs in four groups. Any of the 1.6 GHz LVPECL outputs can be reconfigured as two 250 MHz CMOS outputs. If an application requires LVDS drivers instead of LVPECL drivers, refer to the AD9522-5.

Each group of three outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase offset or coarse time delay to be set.

The AD9520-5 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage of up to 5.5 V. A separate output driver power supply can be from 2.375 V to 3.465 V.

The AD9520-5 is specified for operation over the standard industrial range of ?40°C to +85°C.

FEATURES

Low phase noise, phase-locked loop (PLL)

Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz

1 differential or 2 single-ended reference inputs

Accepts CMOS, LVDS, or LVPECL references to 250 MHz

Accepts 16.62 MHz to 33.3 MHz crystal for reference input

Optional reference clock doubler

Reference monitoring capability

Automatic/ manual reference holdover and reference

switchover modes, with revertive switching

Glitch-free switchover between references

Automatic recovery from holdover

Digital or analog lock detect, selectable

Optional zero delay operation

Twelve 1.6 GHz LVPECL outputs divided into 4 groups

Each group of 3 outputs shares a 1-to-32 divider with

phase delay

Additive output jitter as low as 225 fs rms

Channel-to-channel skew grouped outputs < 16 ps

Each LVPECL output can be configured as 2 CMOS outputs

(for fOUT ≤ 250 MHz)

Automatic synchronization of all outputs on power-up

Manual output synchronization available

SPI- and I2C-compatible serial control port

64-lead LFCSP

Nonvolatile EEPROM stores configuration settings

APPLICATIONS

Low jitter, low phase noise clock distribution

Clock generation and translation for SONET, 10Ge, 10GFC,

Synchronous Ethernet, OTU2/3/4

Forward error correction (G.710)

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

ATE and high performance instrumentation

Broadband infrastructures