AD9761-EB開發(fā)板套件編程器的評(píng)估板-數(shù)模轉(zhuǎn)換器（DAC）規(guī)格書PDF中文資料

AD9761-EB屬于開發(fā)板套件編程器的評(píng)估板-數(shù)模轉(zhuǎn)換器（DAC）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9761-EB評(píng)估板 - 數(shù)模轉(zhuǎn)換器（DAC）該系列產(chǎn)品提供了一種方便的方法，在經(jīng)過驗(yàn)證的設(shè)計(jì)環(huán)境中對(duì)用于將數(shù)字?jǐn)?shù)據(jù)轉(zhuǎn)換為模擬格式的器件進(jìn)行性能或特性評(píng)估。重點(diǎn)器件涵蓋范圍從以適合學(xué)生或愛好者使用的方式實(shí)現(xiàn)的適度功能器件，到適合電信基礎(chǔ)設(shè)施應(yīng)用的高級(jí)器件。

PRODUCT DESCRIPTION

The AD9761 is a complete dual-channel, high speed, 10-bit CMOS DAC. The AD9761 has been developed specifcally for use in wide bandwidth communication applications (e.g., spread spectrum) where digital I and Q information is being processed during transmit operations. It integrates two 10-bit, 40 MSPS DACs, dual 2x interpolation flters, a voltage reference, and digi tal input interface circuitry. The AD9761 supports a 20 MSPS per channel input data rate that is then interpolated by 2x up to 40 MSPS before simultaneously updating each DAC.

The interleaved I and Q input data stream is presented to the digital interface circuitry, which consists of I and Q latches as well as some additional control logic. The data is de-interleaved back into its original I and Q data. An on-chip state machine ensures the proper pairing of I and Q data. The data output from each latch is then processed by a 2x digital interpolation flter that eases the reconstruction flter requirements. The interpolated output of each flter serves as the input of their respective 10-bit DAC.

FEATURES

Complete 10-Bit, 40 MSPS Dual Transmit DAC

Excellent Gain and Offset Matching

Differential Nonlinearity Error: 0.5 LSB

Effective Number of Bits: 9.5

Signal-to-Noise and Distortion Ratio: 59 dB

Spurious-Free Dynamic Range: 71 dB

2x Interpolation Filters

20 MSPS/Channel Data Rate

Single Supply: 3 V to 5.5 V

Low Power Dissipation: 93 mW (3 V Supply @

40 MSPS)

On-Chip Reference

28-Lead SSOP