AK7750中文資料旭化成微電子數(shù)據(jù)手冊PDF規(guī)格書

General Description

The AK7750 is a highly integrated Audio Digital Signal Processor with a stereo audio codec in one chip.

The AK7750 combines an on-chip DSP and an ARM7processor that can be used to create Echo

Cancellation (EC) and Noise Cancellation (NC) functions. These functions make the AK7750 a perfect

choice for hands-free phones thatrequire suppressing acoustic echoand noise. Voice quality and noise

suppression levels can be precisely adjusted by externally setting various parameters. Additionally, no

external Flash, ROM, or RAM is required as memories for Echo and Noise Cancellation are integrated on

chip.

Features

[DSP Block]

?Data Word Length: 24 bit

?Machine Cycle: 27.1 ns (fastest) (768fs at 48 KHz)

?Number of Steps: 768 stepsmax. at fs = 48 KHz

4608 steps max. at fs = 8 KHz

192 steps max. at fs = 192 KHz

?Multiply: 24 x 16 -> 40 bit (enables double precision operation)

?Division: 24 / 24 -> 24 bit or 16 bit

?ALU: 34 bit arithmetic operation (overflow margin 4 bits)

24 bit arithmetic & logic operations

?Shift: 1,2,3,4,6,8,15 Bit Left Shift with indirect shift function

1,2,3,4,8,14,15 bit RightShift with indirect shift function

?Program RAM (PRAM): 768 words x 32 bit

?Coefficient RAM (CRAM): 1024 words x 16 bit

?Data RAM (DRAM): 256 words x 24 bit

?Offset RAM (OFRAM): 48 words x 12 bit

?Delay RAM (DLRAM): 64K bits (following 3 types are selectable):

- 1K words 24 bit

- 1K words 24 bit & 2K words 16 bit (limited pointer capability)

- 4kword 16bit

Data Compression/Expansion circuits for 16 bit data handling are integrated on-chip (Dynamic-range: 23 bit equivalent, S/N+D: 15 bit equivalent (FS)).

- In Hands-free mode, Delay RAM cannot be used.

?Registers: 34 bits x 4 (ACC) [for ALU]

24 bit x 8 (TMP) [for DBUS Interface]

24 bit x 6 stage stacks (PTMP) [for DBUS Interface]

?On-chip ARM7TDMI Processor:

[ADC Block]

?24 Bit 2 Channels (fs: 8 KHz ~ 48 KHz)

?S/N+D: 91 dB (fs = 48 KHz)

?Dynamic Range & S/N: 98 dBA (fs = 48 KHz)

?On-chip DC offset canceling High Pass Filter

[DAC Block]

?24 Bit 2 Channels

?S/N+D: 86 dB (fs = 48 KHz)

?Dynamic Range & S/N: 98 dBA (fs = 48 KHz)

[Input/Output Digital Interface]

?Serial Data Input 8 channels (10 channels with on-board codec.)

?Serial Data Output 6 channels (8 channels with on-board codec.)

?Microprocessor Interface: 1 set of inputs and outputs

[General]

?On-chip PLL

?On-chip EEPROM (AK6512C, AK6514C) Interface

?Single 3.3 V +/- 0.3 V Power Supply

?Operating Temperature Range: -40°C to +85°C

?64-Pin LQFP