BU4042B中文資料羅姆數(shù)據(jù)手冊(cè)PDF規(guī)格書

The BU4042B is a four-circuit D latch with a common clock line and separate data input terminals.

When the polarity input is set to “H”, input (D) is presented to output (Q) as is, as long as the clock input is rising, and when the clock input falls, output (Q) holds input (D) at that point. While the clock input is falling, output (Q) does not change even if input (D) changes.

Also, if the polarity input is set to “L”, input (D) is presented to output (Q) as is, as long as the clock input is at “L” level, and when the clock input goes to “H” level, latching takes place.

Features

1) Low power dissipation.

2) Wide range of operating power supply voltages.

3) High input impedance.

4) High fan-out.

5) Direct drive of 2 L-TTL inputs and 1LS-TTL input.