CD40100BMS中文資料Intersil數(shù)據(jù)手冊PDF規(guī)格書

Description

CD40100BMS is a 32-Stage shift register containing 32 D-type master-slave flip-flops.

The data present at the SHIFT RIGHT INPUT is transferred into the first register stage synchronously with the positive CLOCK edge, provided the LEFT/RIGHT CONTROL is at a low level, the RECIRCULATE CONTROL is at a high level, and the CLOCK INHIBIT is low. If the LEFT/RIGHT CONTROL is at a high level and the RECIRCULATE CONTROL is also high, data at the SHIFT LEFT INPUT is transferred into the 32nd register stage synchronously with the positive CLOCK transition, provided the CLOCK INHIBIT is low. The state of the LEFT/RIGHT CONTROL, RECIRCULATE CONTROL, and CLOCK INHIBIT should not be changed when the CLOCK is high.

Features

? High Voltage Type (20V Rating)

? Fully Static Operation

? Shift Left/Shift Right Capability

? Multiple Package Cascading

? Recirculate Capability

? LIFO of FIFO Capability

? 100 Tested for Quiescent Current at 20V

? 5V, 10V and 15V Parametric Ratings

? Maximum Input Current of 1μA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC

? Noise Margin (Over Full Package/Temperature Range)

?? - 1V at VDD = 5V

?? - 2V at VDD = 10V

?? - 2.5V at VDD = 15V

? Standardized, Symmetrical Output Characteristics ? Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”

Applications

? Serial Shift Registers

? Time Delay Circuits

? Expandable N-Bit Data Storage Stack (LIFO Operation)