CD4017BMS中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書

CD4017BMS and CD4022BMS are 5-stage and 4-stage Johnson counters having 10 and 8 decoded outputs, respectively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times.

Features

? High Voltage Types (20V Rating)

? Fully Static Operation

? Medium-Speed Operation 10MHz (Typ) at VDD = 10V

? Standardized Symmetrical Output Characteristics

? 100 Tested for Quiescent Current at 20V

? 5V, 10V and 15V Parametric Ratings

? Meets All Requirements of JEDEC Tentative Standard Number 13A, “Standard Specifications for Description of ‘B’ Series CMOS Devices”

Applications

? Decade Counter/Decimal Decode Display (CD4017BMS)

? Binary Counter/Decoder

? Frequency Division

? Counter Control/Timers

? Divide-by-N Counting

? For Further Application Information, See ICAN-6166 “COS/MOS MSI Counter and Register Design and Applications”