CD4031BMS中文資料Intersil數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Description

The CD4031BMS is a static shift register that contains 64 D-type, master-slave flip-flop stages and one stage which is a D-type master flip-flop only (referred to as a 1/2 stage).

Features

? High Voltage Type (20V Rating)

? Fully Static Operation: DC to 12MHz (typ.) at VDD - VSS = 15V

? Standard TTL Drive Capability on Q Output

? Recirculation Capability

? Three Cascading Modes:

??? - Direct Clocking for High-Speed Operation

??? - Delayed Clocking for Reduced Clock Drive Requirements

??? - Additional 1/2 Stage for Slow Clocks

? 100 Tested For Quiescent Current at 20V

? Maximum Input Current of 1μA at 18V Over Full Package-Temperature Range;

??? - 100nA at 18V and +25oC

? Noise Margin (Over Full Package Temperature Range):

??? - 1V at VDD = 5V

??? - 2V at VDD = 10V

??? - 2.5V at VDD = 15V

? 5V, 10V and 15V Parametric Ratings

? Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”

Applications

? Serial Shift Registers

? Time Delay Circuits