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CD4071BMS中文資料Intersil數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

CD4071BMS
廠商型號(hào)

CD4071BMS

功能描述

CMOS OR Gate

文件大小

114.68 Kbytes

頁(yè)面數(shù)量

10 頁(yè)

生產(chǎn)廠商 Intersil Corporation
企業(yè)簡(jiǎn)稱

Intersil

中文名稱

Intersil Corporation官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-2-6 21:29:00

CD4071BMS規(guī)格書(shū)詳情

Description

CD4071BMS, CD4072BMS and CD4075BMS OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates.

The CD4071BMS, CD4072BMS and CD4075BMS are supplied in these 14 lead outline packages:

Features

? High-Voltage Types (20V Rating)

? CD4071BMS Quad 2-Input OR Gate

? CD4072BMS Dual 4-Input OR Gate

? CD4075BMS Triple 3-Input OR Gate

? Medium Speed Operation:

- tPHL, tPLH = 60ns (typ) at 10V

? 100 Tested for Quiescent Current at 20V

? Maximum Input Current of 1μA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC

? Standardized Symmetrical Output Characteristics

? Noise Margin (Over Full Package Temperature Range):

? - 1V at VDD = 5V

? - 2V at VDD = 10V

? - 2.5V at VDD = 15V

? 5V, 10V and 15V Parametric Ratings

? Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”

?

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9990
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25630
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TI/德州儀器
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N/A
10350
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TI
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16000
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TI/德州儀器
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12820
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