CD4515BMS中文資料Intersil數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Description

CD4514BMS and CD4515BMS consist of a 4-bit strobed latch and a 4-to-16-line decoder. The latches hold the last input data presented prior to the strobe transition from 1 to 0. Inhibit control allows all outputs to be placed at 0(CD4514BMS) or 1(CD4515BMS) regardless of the state of the data or strobe inputs.

The decode truth table indicates all combinations of data inputs and appropriate selected outputs.

These devices are similar to industry types MC14514 and MC14515.

Features

? High-Voltage Types (20-Volt Rating)

? CD4514BMS Output “High” on Select

? CD4515BMS Output “Low” on Select

? Strobed Input Latch

? Inhibit Control

? 100 Tested for Quiescent Current at 20V

? Maximum Input Current of 1μA at 18V Over Full Pack age Temperature Range; 100nA at 18V and 25oC

? Noise Margin (Full Package-Temperature Range):

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

? 5V, 10V, and 15V Parametric Ratings

? Standardized, Symmetrical Output Characteristics

? Meets all Requirements of JEDEC Tentative Standard No. 13B, Standard Specifications for Description of

‘B’ Series CMOS Devices

Applications

? Digital Multiplexing

? Address Decoding

? Hexadecimal/BCD Decoding

? Program-counter Decoding

? Control Decoder