CS5526集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）規(guī)格書PDF中文資料

CS5526屬于集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）。由凌云邏輯制造生產(chǎn)的CS5526模數(shù)轉(zhuǎn)換器（ADC）模數(shù)轉(zhuǎn)換器（ADC、A/D 或 A 轉(zhuǎn) D）對模擬信號進行采樣，例如由麥克風(fēng)采集的聲音或傳感器的輸出，然后將其轉(zhuǎn)換為數(shù)字信號。一般來說，數(shù)字輸出是二進制補碼二進制數(shù)，與輸入成比例。輸入類型可能是差分、偽差分或單端輸入。模數(shù)轉(zhuǎn)換器可按照位數(shù)、采樣率、輸入數(shù)、接口、轉(zhuǎn)換器數(shù)和架構(gòu)（例如自適應(yīng)增量、雙斜率、折疊、流水線、SAR、三角積分、兩步式）進行選擇。

General Description

The 16-bit CS5525 and the 20-bit CS5526 are highly in tegrated ?ΣA/D converters which include an instrumentation amplifier, a PGA (programmable gain amplifier), eight digital filters, and self and system calibration circuitry.

Features

● Delta-sigma A/D Converter

- Linearity Error: 0.0015FS

- Noise-free Resolution: 18-bits

● Bipolar/Unipolar Input Ranges

- 25 mV, 55 mV, 100 mV, 1 V, 2.5 V and 5 V

● Chopper Stabilized Instrumentation Amplifier

● On-chip Charge Pump Drive Circuitry

● 4 -bit Output Latch

● Simple three-wire serial interface

- SPI? and Microwire? Compatible

- Schmitt Trigger on Serial Clock (SCLK)

● Programmable Output Word Rates

- 3.76 Sps to 202 Sps (XIN = 32.768 kHz)

- 11.47 Sps to 616 Sps (XIN = 100 kHz)

● Output Settles in One Conversion Cycle

● Simultaneous 50/60 HzNoise Rejection

● System and Self-calibration with

Read/Write Registers

● Single +5 V Analog Supply

+3.0 V or +5 V Digital Supply

● Low-power Mode Consumption: 4.9 mW

- 1.8 mW in 1 V, 2.5 V, and 5 V Input Ranges