CY7C025-55JC中文資料賽普拉斯數(shù)據(jù)手冊PDF規(guī)格書

Functional Description

The CY7C024/024A/0241 and CY7C025/0251 are low power CMOS 4K x 16/18 and 8K x 16/18 dual-port static RAMs. Various arbitration schemes are included on the CY7C024/ 0241 and CY7C025/0251 to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory.

Features

■ True dual-ported memory cells, which allow simultaneous reads of the same memory location

■ 4K x 16 organization (CY7C024/024A[1])

■ 4K x 18 organization (CY7C0241)

■ 8K x 16 organization (CY7C025)

■ 8K x 18 organization (CY7C0251)

■ 0.65 micron CMOS for optimum speed and power

■ High speed access: 15 ns

■ Low operating power: ICC = 150 mA (typ)

■ Fully asynchronous operation

■ Automatic power down

■ Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device

■ On-chip arbitration logic

■ Semaphores included to permit software handshaking between ports

■ INT flag for port-to-port communication

■ Separate upper-byte and lower-byte control

■ Pin select for Master or Slave

■ Available in 84-pin (Pb-free) PLCC, 84-pin PLCC, 100-pin (Pb-free) TQFP, and 100-pin TQFP