CY7C027-20AC中文資料賽普拉斯數(shù)據(jù)手冊(cè)PDF規(guī)格書

Functional Description

The CY7C027/028 and CY7C037/038 are low-power CMOS 32K, 64K x 16/18 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 16/18-bit dual-port static RAMs or multiple devices can be combined in order to function as a 32/36-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic.

Features

? True Dual-Ported memory cells which allow simulta neous access of the same memory location

? 32K x 16 organization (CY7C027)

? 64K x 16 organization (CY7C028)

? 32K x 18 organization (CY7C037)

? 64K x 18 organization (CY7C038)

? 0.35-micron CMOS for optimum speed/power

? High-speed access: 12[1]/15/20 ns

? Low operating power

— Active: ICC = 180 mA (typical)

— Standby: ISB3 = 0.05 mA (typical)

? Fully asynchronous operation

? Automatic power-down

? Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device

? On-chip arbitration logic

? Semaphores included to permit software handshaking between ports

? INT flags for port-to-port communication

? Separate upper-byte and lower-byte control

? Dual Chip Enables

? Pin select for Master or Slave

? Commercial and industrial temperature ranges

? Available in 100-pin TQFP

? Pb-Free packages available