CY7C1311JV18中文資料賽普拉斯數(shù)據(jù)手冊(cè)PDF規(guī)格書

Functional Description

The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to eliminate the need to ‘turnaround’ the data bus required with common IO devices.

Features

■ Separate Independent Read and Write Data Ports

? Supports concurrent transactions

■ 300 MHz Clock for High Bandwidth

■ 4-word Burst for reducing Address Bus Frequency

■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 600 MHz) at 300 MHz

■ Two Input Clocks (K and K) for Precise DDR Timing

? SRAM uses rising edges only

■ Two Input Clocks for Output Data (C and C) to minimize Clock Skew and Flight Time mismatches

■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems

■ Single Multiplexed Address Input Bus latches Address Inputs for both Read and Write Ports

■ Separate Port Selects for Depth Expansion

■ Synchronous Internally Self-timed Writes

■ QDR? II Operates with 1.5 Cycle Read Latency when the Delay Lock Loop (DLL) is enabled

■ Operates like a QDR I device with 1 Cycle Read Latency in DLL Off Mode

■ Available in x8, x9, x18, and x36 configurations

■ Full Data Coherency, providing most current Data

■ Core VDD = 1.8 (±0.1V); IO VDDQ = 1.4V to VDD

■ Available in 165-Ball FBGA Package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ Variable Drive HSTL Output Buffers

■ JTAG 1149.1 Compatible Test Access Port

■ Delay Lock Loop (DLL) for Accurate Data Placement