CY7C1329_04中文資料賽普拉斯數(shù)據(jù)手冊PDF規(guī)格書

Features

? Supports 133-MHz bus for Pentium? and PowerPC?

operations with zero wait states

? Fully registered inputs and outputs for pipelined operation

? 64K x 32 common I/O architecture

? Single 3.3V power supply

? Fast clock-to-output times

— 4.2 ns (for 133-MHz device)

— 5.5 ns (for 100-MHz device)

? User-selectable burst counter supporting Intel?

Pentium interleaved or linear burst sequences

? Separate processor and controller address strobes

? Synchronous self-timed writes

? Asynchronous output enable

? JEDEC-standard 100-lead TQFP pinout

? “ZZ” Sleep Mode option and Stop Clock option