CY7C1361B-100AJC中文資料賽普拉斯數(shù)據(jù)手冊PDF規(guī)格書

Functional Description[1]

The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

Features

? Supports 133-MHz bus operations

? 256K X 36/512K X 18 common I/O

? 3.3V –5 and +10 core power supply (VDD)

? 2.5V or 3.3V I/O supply (VDDQ)

? Fast clock-to-output times

— 6.5 ns (133-MHz version)

— 7.5 ns (117-MHz version)

— 8.5 ns (100-MHz version)

? Provide high-performance 2-1-1-1 access rate

? User-selectable burst counter supporting Intel? Pentium? interleaved or linear burst sequences

? Separate processor and controller address strobes

? Synchronous self-timed write

? Asynchronous output enable

? Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA and 165-ball fBGA packages

— Both 2 and 3 Chip Enable Options for TQFP

? JTAG boundary scan for BGA and fBGA packages

? “ZZ” Sleep Mode option