CY7C1443AV33中文資料賽普拉斯數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Functional Description

The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

Features

■ Supports 133-MHz bus operations

■ 1 M × 36/2 M × 18/512 K × 72 common IO

■ 3.3 V core power supply

■ 2.5 V or 3.3 V IO power supply

■ Fast clock-to-output times

? 6.5 ns (133-MHz version)

■ Provide high-performance 2-1-1-1 access rate

■ User-selectable burst counter supporting Intel? Pentium? interleaved or linear burst sequences

■ Separate processor and controller address strobes

■ Synchronous self-timed write

■ Asynchronous output enable

■ CY7C1441AV33, CY7C1443AV33 available in

JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and

non Pb-free 165-ball FBGA package. CY7C1447AV33

available in Pb-free and non Pb-free 209-ball FBGA package

■ IEEE 1149.1 JTAG-Compatible Boundary Scan

■ “ZZ” Sleep Mode option