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CY7C1663KV18-550BZXC集成電路(IC)的存儲(chǔ)器規(guī)格書(shū)PDF中文資料

CY7C1663KV18-550BZXC
廠商型號(hào)

CY7C1663KV18-550BZXC

參數(shù)屬性

CY7C1663KV18-550BZXC 封裝/外殼為165-LBGA;包裝為托盤;類別為集成電路(IC)的存儲(chǔ)器;產(chǎn)品描述:IC SRAM 144MBIT PARALLEL 165FBGA

功能描述

144-Mbit QDR? II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)

封裝外殼

165-LBGA

文件大小

779.75 Kbytes

頁(yè)面數(shù)量

31 頁(yè)

生產(chǎn)廠商 CypressSemiconductor
企業(yè)簡(jiǎn)稱

Cypress賽普拉斯

中文名稱

賽普拉斯半導(dǎo)體公司官網(wǎng)

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更新時(shí)間

2025-2-23 10:10:00

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CY7C1663KV18-550BZXC規(guī)格書(shū)詳情

Functional Description

The CY7C1663KV18, and CY7C1665KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices.

Features

■ Separate independent read and write data ports

? Supports concurrent transactions

■ 550-MHz clock for high bandwidth

■ Four-word burst for reducing address bus frequency

■ Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz

■ Available in 2.5-clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

? SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Single multiplexed address input bus latches address inputs for read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ Quad data rate (QDR?) II+ operates with 2.5-cycle read latency when DOFF is asserted high

■ Operates similar to QDR I device with one cycle read latency when DOFF is asserted low

■ Available in × 18, and × 36 configurations

■ Full data coherency, providing most current data

■ Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD [1]

? Supports both 1.5-V and 1.8-V I/O supply

■ High-speed transceiver logic (HSTL) inputs and variable drive HSTL output buffers

■ Available in 165-ball fine-pitch ball grid array (FBGA) package (15 × 17 × 1.4 mm)

■ Offered in Pb-free package

■ JTAG 1149.1 compatible test access port

■ Phase locked loop (PLL) for accurate data placement

產(chǎn)品屬性

  • 產(chǎn)品編號(hào):

    CY7C1663KV18-550BZXC

  • 制造商:

    Cypress Semiconductor Corp

  • 類別:

    集成電路(IC) > 存儲(chǔ)器

  • 包裝:

    托盤

  • 存儲(chǔ)器類型:

    易失

  • 存儲(chǔ)器格式:

    SRAM

  • 技術(shù):

    SRAM - 同步,QDR II+

  • 存儲(chǔ)容量:

    144Mb(8M x 18)

  • 存儲(chǔ)器接口:

    并聯(lián)

  • 電壓 - 供電:

    1.7V ~ 1.9V

  • 工作溫度:

    0°C ~ 70°C(TA)

  • 安裝類型:

    表面貼裝型

  • 封裝/外殼:

    165-LBGA

  • 供應(yīng)商器件封裝:

    165-FBGA(15x17)

  • 描述:

    IC SRAM 144MBIT PARALLEL 165FBGA

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫(kù)存 備注 價(jià)格
INFINEON/英飛凌
23+
PG-BGA-165
28611
為終端用戶提供優(yōu)質(zhì)元器件
詢價(jià)
Cypress Semiconductor Corp
24+
165-FBGA(15x17)
56200
一級(jí)代理/放心采購(gòu)
詢價(jià)
CYPRESS/賽普拉斯
20+
FBGA-165
1050
優(yōu)惠訂貨,先確認(rèn)交期
詢價(jià)
Cypress Semiconductor Corp
23+
165-FBGA15x17
7300
專注配單,只做原裝進(jìn)口現(xiàn)貨
詢價(jià)
Cypress
21+
25000
原廠原包 深圳現(xiàn)貨 主打品牌 假一賠百 可開(kāi)票!
詢價(jià)
CYPRESS
23+
NA
1221
專業(yè)電子元器件供應(yīng)鏈正邁科技特價(jià)代理QQ1304306553
詢價(jià)
CYPRESS
2024+
N/A
70000
柒號(hào)只做原裝 現(xiàn)貨價(jià)秒殺全網(wǎng)
詢價(jià)
CYPRESS
ROHS+Original
NA
1221
專業(yè)電子元器件供應(yīng)鏈/QQ 350053121 /正納電子
詢價(jià)
CYPRESS(賽普拉斯)
23+
LBGA165
7350
現(xiàn)貨供應(yīng),當(dāng)天可交貨!免費(fèi)送樣,原廠技術(shù)支持!!!
詢價(jià)
Cypress Semiconductor Corp
21+
780-BBGA
55
進(jìn)口原裝!長(zhǎng)期供應(yīng)!絕對(duì)優(yōu)勢(shì)價(jià)格(誠(chéng)信經(jīng)營(yíng)
詢價(jià)