CY7C4275-10ASI中文資料賽普拉斯數(shù)據(jù)手冊(cè)PDF規(guī)格書

Functional Description

The CY7C4275/85 are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to the CY7C42X5 Synchronous FIFO family. The CY7C4275/85 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.

Features

? High-speed, low-power, first-in first-out (FIFO)

memories

? 32K x 18 (CY7C4275)

? 64K x 18 (CY7C4285)

? 0.5 micron CMOS for optimum speed/power

? High-speed 100-MHz operation (10-ns read/write cycle times)

? Low power

— ICC=50 mA

— ISB = 2 mA

? Fully asynchronous and simultaneous read and write operation

? Empty, Full, Half Full, and programmable Almost Empty and Almost Full status flags

? TTL compatible

? Retransmit function

? Output Enable (OE) pin

? Independent read and write enable pins

? Center power and ground pins for reduced noise

? Supports free-running 50 duty cycle clock inputs

? Width Expansion Capability

? Depth Expansion Capability

? 68-pin PLCC and 64-pin 10x10 TQFP

? Pin-compatible density upgrade to CY7C42X5 families

? Pin-compatible density upgrade to IDT72205/15/25/35/45