DM74LS138N集成電路（IC）的信號開關多路復用器解碼器規(guī)格書PDF中文資料

General Description

These Schottky-clamped circuits are designed to be used

in high-performance memory-decoding or data-routing

applications, requiring very short propagation delay times.

In high-performance memory systems these decoders can

be used to minimize the effects of system decoding. When

used with high-speed memories, the delay times of these

decoders are usually less than the typical access time of

the memory. This means that the effective system delay

introduced by the decoder is negligible.

The DM74LS138 decodes one-of-eight lines, based upon

the conditions at the three binary select inputs and the

three enable inputs. Two active-low and one active-high

enable inputs reduce the need for external gates or inverters

when expanding. A 24-line decoder can be implemented

with no external inverters, and a 32-line decoder

requires only one inverter. An enable input can be used as

a data input for demultiplexing applications.

The DM74LS139 comprises two separate two-line-to-fourline

decoders in a single package. The active-low enable

input can be used as a data line in demultiplexing applications.

All of these decoders/demultiplexers feature fully buffered

inputs, presenting only one normalized load to its driving

circuit. All inputs are clamped with high-performance

Schottky diodes to suppress line-ringing and simplify system

design.

Features

n Designed specifically for high speed:

Memory decoders

Data transmission systems

n DM74LS138 3-to-8-line decoders incorporates 3 enable

inputs to simplify cascading and/or data reception

n DM74LS139 contains two fully independent 2-to-4-line

decoders/demultiplexers

n Schottky clamped for high performance

n Typical propagation delay (3 levels of logic)

DM74LS138 21 ns

DM74LS139 21 ns

n Typical power dissipation

DM74LS138 32 mW

DM74LS139 34 mW